Noxim

Abstract

Noxim is a Network-on-Chip (NoC) simulator developed in SystemC and freely downloadable from sourceforge under GPL license terms. Noxim is intended for those who want to explore the design space spanned by the different parameters of a NoC for the analysis and evaluation of a large set of quality indices including delay, throughput, energy consumption, etc. Precisely, the configurable parameters that can be tuned are as follows:

  1. Network size
  2. Buffers depth
  3. Packets size distribution
  4. Routing algorithm (XY, West-First, North-Last, Negative-First, Odd-Even, DyAD, Table-based)
  5. Selection policy (random, buffer-level, Nwighbors-on-Path
  6. Packet injection rate
  7. Packet injection distribution (Poisson, Burst, Self-similar)
  8. Traffic type (Uniform, Transpose 1, Transpose 2, custom)
  9. Hot-spot traffic distribution

The avaluation metrics that can be measured are as follows:

  1. Received packets/flits
  2. Global average delay
  3. Global average throughput
  4. Max/min global delay
  5. Total energy consumption
  6. Per-communication delay, throughput, energy, etc.

Download

Click here to download the last version of noxim. Comments and suggestions can be sent to the authors:

  1. Fabrizio Fazzino [email] [web]
  2. Maurizio Palesi [email] [web]
  3. Davide Patti [email] [web]

References

The following papers have been developed using noxim as NoC simulator.

  1. M. Palesi, R. Holsmark, S. Kumar, V. Catania. Application Specific Routing Algorithms for Networks on Chip. Accepted for publication in IEEE Transactions on Parallel and Distributed Systems.
  2. A. Mejia, M. Palesi, J. Flich, S. Kumar, P. Lopez, R. Holsmark and J. Duato. Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. Accepted for publication in IEEE Transactions on on Very Large Scale Integration Systems.
  3. G. Ascia, V. Catania, M. Palesi, D. Patti. Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE Transactions on Computers, 57(6), pp. 809-820, June 2008.
  4. D. Frazzetta, G. Dimartino, M. Palesi, S. Kumar, V. Catania. Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. 11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 18-25, Sep. 3-5, 2008, Como, Italy.
  5. R. Tornero, J. M. Orduna, M. Palesi, J. Duato. A Communication-Aware Topological Mapping Technique for NoCs. International Conference on Parallel and Distributed Computing, pp. 910-919, August 26-29th, 2008, Las Palmas de Gran Canaria, Spain.
  6. M. Palesi, G. Longo, S. Signorino, S. Kumar, R. Holsmark, V. Catania. Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. IEEE International Symposium on Networks-on-Chip, pp. 97-106, 7th-11th April 2008, Newcastle University, UK.
  7. G. Longo, S. Signorino, M. Palesi, S. Kumar, R. Holsmark, V. Catania. Bandwidth Aware Routing Algorithms for Networks-on-Chip. 2nd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip. Goteborg, Sweden, January 27, 2008.
  8. R. Tornero, J. M. Orduna, M. Palesi, J. Duato. A Communication-Aware Task Mapping Technique for NoCs. 2nd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip. Goteborg, Sweden, January 27, 2008.
  9. M. Palesi, S. Kumar, R. Holsmark, V. Catania. Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IEEE International Parallel and Distributed Processing Symposium, pp. 1-8, Long Beach, CA, March 2007.
  10. G. Ascia, V. Catania, M. Palesi, D. Patti. Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. Fourth IEEE Workshop on Embedded Systems for Real Time Multimedia, pp. 79-84. Seoul, Korea, October 26-27, 2006.
  11. M. Palesi, R. Holsmark, S. Kumar, V. Catania. A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems. International Conference on Hardware-Software Codesign and System Synthesis, pp. 142-147. Seoul, Korea, October 22-25, 2006.
  12. M. Palesi, S. Kumar, R. Holsmark. A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. SAMOS VI Workshop: Embedded Computer Systems: Architectures, Modeling, and Simulation, pp. 373-384. Samos, Greece, July 17-20, 2006.
  13. G. Ascia, V. Catania, M. Palesi, D. Patti. A New Selection Policy for Adaptive Routing in Network on Chip. International Conference on Electronics, Hardware, Wireless and Optical Communications. Madrid, Spain, February 15-17, 2006.